HEMANTH KALAIYAPPAN

DFT Engineer

Final-Year Electronics and Communication Engineering student specializing in Design-for-Test (DFT), with hands-on training in Siemens Tessent flows including Scan Insertion, ATPG, EDT/OCC, MBIST, and UVM-based Verification.

:: VIEW PROJECTS :: VIEW RESUME :: HIRE ME

10x EDT Compression Ratio

98.18% Functional Coverage

2026 Expected Graduation

8.47 CGPA

:: TECHNICAL HIGHLIGHTS

DFT

Scan Insertion
ATPG
EDT Compression
OCC Integration
MBIST
DFT DRC

Verification

SystemVerilog
UVM
Assertions
Functional Coverage
Scoreboarding

Tools

Siemens Tessent
ModelSim
Yosys
Vivado
Linux
Git/GitHub
TCL

:: FEATURED PROJECT

Secure APB Register & System Watchdog Subsystem

Multi-clock secure subsystem featuring APB interface, watchdog timer, hardened FSM architecture, shadow-register protection, and complete UVM-based verification environment.

SystemVerilog UVM APB Multi-Clock

98.18% functional coverage
82 scoreboard & assertion checks verified
Verification plan and test cases completed

VIEW CASE STUDY

// COLOPHON

This portfolio is engineered with semantic HTML5, custom CSS variables, and vanilla JavaScript, with performance, keyboard access, and high-contrast modes considered throughout.

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