:: TRAINING & EXPERIENCE
10x
EDT Compression
2
Training Programs
2026
Graduation
VLSI Design Flow Intern
NIELIT
- Completed end-to-end RTL-to-GDSII VLSI Design Flow training.
- Designed RTL using Verilog HDL for an 8-bit ALU and sequence detector; performed functional verification.
- Synthesized designs using Yosys and performed timing analysis with OpenSTA; achieved timing closure at 50 MHz with zero setup/hold violations.
- Explored physical design concepts using Magic (floorplanning, placement, routing).
- Generated gate-level netlist and verified equivalence against RTL.
- Tools used: Yosys, OpenSTA, Magic, Verilog HDL.
DFT Trainee
VLSIGURU Institute
- Hands-on training using Siemens Tessent for Scan, MBIST, EDT/OCC, and ATPG flows.
- Performed Scan Insertion and Scan Stitching across hierarchical and flat designs.
- Executed DFT DRC analysis and resolved setup, hold, and rule violations.
- Implemented MBIST insertion and memory testing configurations.
- Deployed EDT compression and OCC integration for at-speed testing.
- Generated ATPG patterns and analyzed fault coverage metrics.
- Implemented and script-configured DFT structures on design blocks up to 42K flip-flops.
- Achieved >95% stuck-at fault coverage through ATPG pattern optimization and scan chain balancing.
// TECHNICAL HIGHLIGHTS
Scan Insertion
ATPG
MBIST
EDT/OCC
DFT DRC
Hierarchical DFT Flow
Flat DFT Flow
42K FF Design
RTL-to-GDSII
// DEBUGGING & ANALYSIS
- Identified and resolved DFT DRC violations including scan chain conflicts and clock domain crossing issues
- Analyzed ATPG coverage reports to identify untestable faults and improved coverage through test point insertion
- Debugged simulation mismatches between functional and scan mode operation
- Performed scan chain diagnosis to isolate and fix chain failures
// CURRENT OBJECTIVE
Seeking full-time opportunities in Design-for-Test (DFT), VLSI Design, and Verification Engineering where I can apply Siemens Tessent based DFT knowledge, digital design fundamentals, and verification skills.