STATUS: COMPLETED
COMPLETED: DEC 2025
Secure APB Register & Watchdog Subsystem
Designed and verified a multi-clock secure subsystem featuring
APB interface, watchdog timer, hardened FSM, shadow-register
protection, and security monitoring logic.
Achieved 98.18% functional coverage using a complete
UVM verification environment.
SystemVerilog
UVM
APB
Assertions
:: ACCESS CASE STUDY
STATUS: COMPLETED
COMPLETED: FEB 2026
Hierarchical DFT Training Flow
Implemented a complete Siemens Tessent DFT flow on a hierarchical
training design with parent and child cores.
Executed Scan Stitching, MBIST insertion, DFT DRC cleanup,
EDT compression, OCC integration, ATPG setup,
and fault coverage analysis across the full design hierarchy.
Achieved >95% stuck-at fault coverage with EDT compression ratio of 10x,
generating ~500 test patterns across 32 scan chains and 3 clock domains.
Tessent
Scan
ATPG
MBIST
32 Scan Chains
10x Compression
>95% Coverage
STATUS: COMPLETED
COMPLETED: APR 2026
Block-Level Flat DFT Flow
Executed a complete DFT implementation flow on a flat training
design utilizing test design blocks.
Performed MBIST insertion, Scan Stitching, EDT/OCC integration,
ATPG execution, coverage analysis, and DFT violation debugging
to achieve targeted fault coverage.
Achieved >95% stuck-at fault coverage on test design blocks,
resolving post-synthesis DFT DRC violations through scan chain reordering
and test point insertion.
Tessent
EDT/OCC
ATPG
Block-Level DFT
DRC Cleanup
64 Scan Chains
>95% Coverage
STATUS: COMPLETED
COMPLETED: AUG 2025
RTL-to-GDSII Design Flow
Designed RTL in Verilog, performed synthesis using Yosys,
conducted static timing analysis with OpenSTA,
and explored physical design concepts using Magic
through the NIELIT VLSI Design Flow training program.
Verilog
Yosys
OpenSTA
Magic