:: SYSTEM INFORMATION

// BIO_DATA

Hemanth Kalaiyappan — Final-Year Electronics and Communication Engineering student specializing in Design-for-Test (DFT), with hands-on experience in industry-standard EDA flows.

Completed Siemens Tessent-based DFT training covering full Scan Insertion, ATPG, EDT/OCC, MBIST, DFT DRC analysis, and fault coverage optimization on flat and hierarchical design blocks.

Also experienced in SystemVerilog RTL design, UVM Verification, multi-clock digital systems, and RTL-to-GDSII flows. Focused on building reliable, testable silicon through structured DFT methodologies.

// TECHNICAL_STACK

// PROFICIENT

Scan Insertion ATPG EDT Compression OCC MBIST DFT DRC SystemVerilog Siemens Tessent

// FAMILIAR

UVM Assertions Functional Coverage Verilog TCL ModelSim Vivado Yosys Linux Git

// EDUCATION

Sri Venkateswara College of Engineering (SVCE)

B.E. Electronics and Communication Engineering
CGPA: 8.47
Expected Graduation: 2026

Relevant Coursework: VLSI Design, Digital Electronics, Computer Architecture, Embedded Systems, Analog Electronics, Verification & Testing

// DFT_HIGHLIGHTS

Hierarchical DFT Flow Flat DFT Flow 98.18% Coverage DRC Violation Resolution Secure Register & Watchdog Subsystem

// CURRENT_OBJECTIVE

Seeking full-time opportunities as a DFT Engineer, VLSI Design Engineer, or Verification Engineer where I can contribute to silicon testability, verification methodology, and semiconductor product development.